The present invention relates to semiconductor packaging and more particularly to a semiconductor device having staggered leads and improved lead pitch.
A factor limiting the density of leads (number of leads per unit length) that a semiconductor device such as a quad flat leaded package (QFP) of a given size can contain is lead pitch. Native lead pitch (LP) is essentially the sum of native lead width (LW) plus native spacing between two leads (LS). A wider lead pitch avoids or at least reduces risk of circuit shortage and improves solderability when the semiconductor device is mounted using a surface-mount technology (SMT) process. It also allows wider leads to be formed, which in turn reduces incidence of lead stress and distortion. A narrower lead pitch on the other hand facilitates greater leads density.
Therefore it would be desirable to provide a semiconductor device that has a wider lead pitch without sacrificing leads density.